1. Field of the Invention
The present invention relates to a voltage dividing circuit which utilizes charge redistribution by means of serially connected capacitors and a voltage dividing circuit which comprises serially connected resistors. More particularly, it relates to a voltage dividing circuit which minimizes the influence of the characteristic difference among the capacitors or resistors on the output voltage, i.e. a fraction of the total voltage. Further, the present invention relates to a voltage dividing circuit wherein each of the capacitors is connected alternately to power sources to obtain an average output voltage.
2. Description of the Prior Art
In recent years, the integration density of integrated circuits has been increasing. Along with the increase in integration density there is a trend in which various elements having different functions are formed on a single semiconductor chip. For example, a logic circuit system, which was once comprised of tens of semiconductor chips, is now made of only one semiconductor chip. This has successfully improved the cost-performance relationship of logic circuit systems. Now the requirement has arisen that a one-chip integrated circuit should process analog input data. Position data supplied to control devices, for example, are mainly analog data. So are most output data from sensors. In order to achieve a complicated sequence of control steps it is necessary to convert such analog data into digital data. It is therefore desired that analog-digital converters should be formed on a semiconductor chip using digital circuits.
Moreover, what is increasingly needed are digital-analog converters and analog-digital converters of high speed and high precision. This is because audio apparatus, PCM communication systems, video tape recorders and the like, which have conventionally processed analog data, are now being modified to process digital data. Therefore, it is preferred that a high-speed analog-digital or digital-analog conversion be performed. A digital circuit can easily enhance the accuracy of calculation merely by increasing the number of bits for each piece of digital data and can increase the operation speed. A digital circuit is required which will operate at a higher accuracy and with a higher speed than an analog circuit. This is being made possible by the technical researches and developments which are under way at present. In view of this trend it is strongly desired that the interface devices, i.e. digital-analog converters and analog-digital converters, and switched capacitor filters should be improved so that they may operate at a higher speed and may process data with a higher accuracy.
MOS integrated circuits which have a high integration density are used as large-scale logic integrated circuits in most cases. This is because they consume far less power than bipolar transistor integrated circuits and have a higher integration density. An MOS IC and an MOS LSI are advantageous in two respects. First, they can use MOS capacitors. Secondly, they can use voltage, current or charge as variables, while a bipolar transistor integrated circuit can use either resistance or current as variables.
Previously, in order to obtain analog data by a digital-analog conversion (DAC) or by internal DAC for analog-digital conversion (ADC), a current dividing circuit such as that shown in FIG. 1 was used in a bipolar transistor integrated circuit. The circuit of FIG. 1 comprises R-2R ladder resistors, thereby using a current branch circuit.
In the circuit of FIG. 1, the first and second resistors from the right, which have a resistance R, are connected in series. The sum of their resistances is thus 2R. The series circuit of these resistors is connected in parallel to the rightmost one of the other group of resistors whose resistance is 2R. The combined resistance 2R of the series circuit and the resistance 2R of the rightmost resistor is therefore R. The circuit having this sum resistance R is connected in series to the third resistor from the right, which has a resistance R, and the sum of the resistance is thus 2R. The circuit having this resistance 2R is connected in series to the second one of the resistors having a resistance 2R, counted from the right. The sum of resistance is therefore R. The remaining resistors, some having a resistance R and the other having a resistance 2R, are connected in the same way. Accordingly, the current flowing through the first and second resistors from the right which have a resistance R is i, the current flowing through the right most resistor having a resistance 2R is also i, the current flowing through the third resistor from the right which has a resistance 2R is 2i, the current flowing through the second resistor from the right which has a resistance 2R is also 2i, and so forth. The current distribution thus obtained is: i, 2i, 4i, 8, . . . . This is equivalent to current distribution of i, i/2, i/4, i/8, . . . when the power source current is taken as reference. An output current of the circuit is taken through a transistor switch or the like by adding selected ones of the currents flowing through the respective resistors. This is how an analog signal, i.e. the output current, which corresponds to a digital input signal, is obtained. The circuit shown in FIG. 1 is used chiefly for a bipolar transistor integrated circuit. This is because a bipolar transistor, whose collector-emitter conductance is relatively large, may be used as a switching element since its conduction resistance is negligibly low as compared with the resistance of any resistors of the current dividing circuit such as shown in FIG. 1. By contrast, a MOS transistor has a output conductance smaller than that of a bipolar transistor. If its conduction resistance is to be made sufficiently low, it has to be too large to be suitable for an element of an integrated circuit and, therefore, it can not be applied to practical IC use.
For the reason mentioned above, a voltage dividing circuit such as that shown in FIG. 2 or FIG. 3 is used in an MOS transistor integrated circuit. The resistor circuit of FIG. 2 uses voltage as variable and the capacitor matrix circuit of FIG. 3 uses charge as variable.
The voltage dividing circuit shown in FIG. 2 comprises resistors R.sub.1 to R.sub.n which have the same resistance and which are connected in series. The reference voltage V.sub.REF is divided into n equal fractions, and an output voltage (or potential) V.sub.out is taken from a selected one of the nodes N.sub.1, N.sub.2, N.sub.3, . . . of the resistors R.sub.1 to R.sub.n. Current I is given by: ##EQU1##
The output voltage V.sub.out from the j-th resistor is given by: ##EQU2##
The value of analog voltage V.sub.out depends on the accuracy of each resistor used. The current I is indeed constant, but the maximum output voltage error .DELTA.V.sub.out will be: EQU .DELTA.V.sub.out =I.multidot.(n/2).DELTA.R.
where .DELTA.R is the difference in resistance among the resistors R.sub.1 to R.sub.n.
The capacitor matrix circuit of FIG. 3 comprises capacitors C.sub.0, C.sub.0, 2C.sub.0, 4C.sub.0 and 8C.sub.0, switches S.sub.1 to S.sub.5 and two power sources V.sub.1 and V.sub.2 where V.sub.1 has a higher potential than V.sub.2. Each of the switches S.sub.1 to S.sub.5 have one movable contact and two stationary contacts. When the switches S.sub.1 to S.sub.4 have their movable contacts connected to their left stationary contacts and the switch S.sub.5 has its movable contact connected to its right stationary contact, there will be formed a circuit of the parallel capacitors C.sub.0, C.sub.0, 2C.sub.0 and 4C.sub.0 in series with the capacitor 8C.sub.0. The total capacitance of the circuit is 16C.sub.0. The output voltage V.sub.out is therefore (V.sub.1 -V.sub.2)/2, i.e. the voltage exactly halfway between V.sub.1 and V.sub.2. This output voltage is expressed in potential as: (V.sub.1 -V.sub.2)/2+V.sub.2 =(V.sub.1 +V.sub.2)/2. Suppose the movable contact of the switch S.sub.4 is connected to the right stationary contact. Then, there will be formed a circuit of the parallel capacitors C.sub.0, C.sub.0 and 2C.sub.0 in series with the parallel capacitors 4C.sub.0 and 8C.sub.0. The output voltage V.sub.out will then be (V.sub.1 +3V.sub.2)/4 which is higher than V.sub.2 by (V.sub.1 -V.sub.2)/4. Similarly, various output voltages V.sub.out which are 15/16, 14/16, 13/16, . . . of (V.sub.1 -V.sub.2) will be obtained by connecting the movable contacts of the switches S.sub.1 to S.sub.5 to the right or left stationary contacts. (Various potentials each of which is the sum of the output voltage V.sub.out and voltage V.sub.2 will be obtained).
For the voltage dividing circuit of FIG. 3, it is required that every capacitor should have a correct capacitance ratio to any other capacitor. The output voltage V.sub.out would otherwise be erroneous. This will be described with reference to FIG. 4.
As evident from the principle of charge redistribution, the output voltage V.sub.out of the circuit shown in FIG. 4 is given by: ##EQU3## where V.sub.1 and V.sub.2 are voltages applied to two input terminals and C.sub.T is the sum of C.sub.01, C.sub.02 and the initial charge Q.sub.0. If the capacitance of the capacitor C.sub.01 differs by .DELTA.C.sub.0 from the capacitance of the capacitor C.sub.02 and the initial charge Q.sub.0 is neglected, the output voltage V.sub.out will then be: ##EQU4## The output error .DELTA.V.sub.out will be: ##EQU5##
The initial charge Q.sub.0 is almost held constant, because this charge is periodically compensated via an external switch (not shown) which is connected to the output terminal V.sub.out and a reference voltage.
In a capacitor matrix circuit having more capacitor (e.g. N capacitors), C.sub.T and .DELTA.V.sub.out are given by: ##EQU6##
Obviously, both C.sub.T and V.sub.out are similar to those in a series circuit of resistors. Hence, in order to make the output voltage V.sub.out as accurate as possible, it would be necessary to have accurate capacitances for the respective capacitors. In view of the manufacturing techniques available at present, however, a .DELTA.C.sub.0 /C.sub.0 of 1% persistently exists as an error.
The above described conventional voltage, current or charge dividing circuits have such a drawback in that the divisional error increases with an increase in the number of data bits in a digital signal due to the fact that the accuracy of a division of voltage, current or charge depends on the accuracy with which each resistor or capacitor was manufactured. In the circuit of FIG. 2, for example, a total current I is constant as expressed by the equation of ##EQU7## but each node voltage V.sub.m is expressed by the equation of ##EQU8## thereby producing an error in the output voltage V.sub.m that is the sum of the errors .DELTA.R of the resistances of the respective resistors.
The known current dividing circuits and voltage dividing circuits described above need to have more and more elements if they are to improve the accuracy of the output signal. The R-2R ladder circuit of FIG. 1, for example, needs an additional pair of resistors having resistances R and 2R, respectively, in order to process an input digital signal having an additional bit. The voltage dividing circuit of FIG. 2 for an MOS transistor integrated circuit, for which an R-2R ladder circuit is useless, needs 2.sup.N resistors in order to process an input N-bit digital signal. The voltage dividing circuit shown in FIG. 3 needs 2.sup.N capacitors in order that the capacitors connected in parallel provide an output voltage corresponding to any input N-bit digital signal. In short, the known circuits must have a great number of resistors or capacitors in order to improve the resolution with which to process input digital signals. These resistors or capacitors are large and need to be made with high precision unlike those used in a digital logic circuit. In consequence, the known circuit is unavoidably large and difficult to manufacture.